This lowers immediate capital investment and provides for future growth as devices evolve from generation to generation, integrating more high-speed interfaces or achieving higher processing speeds. Each pin operates independently, enabling parallel processing for maximum multi-site efficiency. Compatible with Agilent Ce-channels Protects your investment in equipment, people and training Additional Detail Up to pins The Pin Scale offers 32 pins per card, which is twice the density of the Ce- and P-model digital cards. Add to collection s Add to saved. Available per-pin licenses for memory depth: And this must all be done at a lower costof-test than last year because of ongoing price erosion. Per-pin speed scalability from Mbps to Mbps provides the performance needed to test a wide range of interfaces, including USB2. This enables the Agilent to offer the following pin counts:

Up to pins Support of multi-site for high pin count devices reduces cost-of-test. Add this document to collection s. As test needs change to accommodate a new class of device or next-generation performance, the Pin Scale can be instantly reconfigured through software to maximize the lifetime of your investment. You can add this document to your study collection s Sign in Available only to authorized users. This lowers immediate capital investment and provides for future growth as devices evolve from generation to generation, integrating more high-speed interfaces or achieving higher processing speeds. Per-pin software licenses for speed and memory depth mean you add just the performance you need, when you need it. The Pin Scale offers broad scalability starting at Mbps for low cost, low performance needs and scaling to Mbps for higher performance demands — all with a single digital card. Reconfiguration is done instantly when the test program is loaded, ensuring no downtime.

This unprecedented flexibility allows the Agilent to match the next device to be tested, instantly. This lowers immediate capital investment and provides for future growth as devices evolve from generation to generation, integrating more high-speed interfaces or achieving higher processing speeds.

You can add this document to your study collection s Sign in Available only to authorized users. With trainimg licenses to enable the different speed and memory performance levels — part of the industry-first Agilent InstaPin performance library — the Pin Scale digital card can be configured to match the agileny requirements, pin-by-pin, resulting in the lowest cost of test. This unmatched performance also enables testing of logic cores in a range of applications while maintaining headroom for increasing processing speeds.

Agilent 93000 Pin Scale 800

The Pin Scale protects your investment through expanded scalability, which provides the performance needed to test a wide variety of devices now and into the future. The Pin Scale features a Test Processor-Per-Pin architecture, which allows all processing to occur locally in the card, and in parallel across pins, providing maximum parallel efficiency.

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This flexibility can be especially important for embedded memory, microprocessor and protocol-based communications applications. Product Summary Per-pin scalability up to Mbps High agilejt digital card with per-pin scalability up to Mbps offers the lowest cost SOC test in production. The value of parallel test, however, depends on its efficiency. In addition, each digital pin operates in parallel, maximizing multi-site efficiency.

For printed directions on Preparing for Registration. Unified memory approach The entire amount of purchased memory is available for both test vectors and sequencer instructions for maximum flexibility.

Because the reconfiguration is accomplished via software, no hardware is moved, which eliminates the need to recalibrate and eliminates the risk of hardware damage during movement. You can add this document to your saved list Sign in Available only to authorized users. Test Processor-Per-Pin architecture Localizing all test processing instead of using centralized resources results in minimal measurement overhead and higher throughput.

Provides performance headroom for the future, protecting your investment. Reconfiguration is done instantly when the test program is loaded, ensuring no downtime.

Available per-pin licenses for memory depth: Add this document to saved. Each use of the Pin Scale can be scaled over its wide memory depth and speed range through per-pin software licenses, which provides the lowest cost of test by allowing the test system to be configured to match device requirements, pin-by-pin. The Pin Scale offers broad scalability starting at Mbps for low cost, low trainihg needs and scaling to Mbps for higher performance demands — trajning with a single digital card.

This enables the Agilent to agklent the following pin counts: Provides performance for high speed interface test, such as DDR, operating over Mbps. Compatible with Agilent Ce-channels Protects your investment in equipment, xoc and training Additional Detail Up to pins The Pin Scale offers 32 pins per card, which is twice the density of the Ce- and P-model digital cards.

An uncertain future demands the ability to upgrade quickly to meet the next performance challenge while continuing to reduce cost-of-test. Performance for next-generation SOC devices With digital speeds up to Mbps and memory up to MB Trainkng Mode on each pin, the Trainkng Scale delivers the performance demanded by next-generation devices.

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Unified memory approach The unified memory approach pools memory for both sequence instructions and vectors. Each pin operates independently, enabling parallel processing for maximum multi-site efficiency.

And this must all be done at a lower costof-test than last teaining because of ongoing price erosion. Agilent InstaPin also maximizes asset utilization because the per-pin licenses for speed and memory depth of Seriea Scale digital cards can float between pins on a card, cards in a tester and testers on a test floor or different production facilities around the world.

Flexible waveform sox for high-speed applications. Agilent Pin Scale Product Overview Industry Challenges Consumer demand for more capability and connectivity in a single product is driving the need for more functionality, faster processing and higher speed interfaces in next-generation System-on-a-Chip SOC and System-in-Package SIP devices.

To test these devices, a test system must have the capability to address a range of performance challenges: Also beneficial to generate low jitter high-speed clock signals.

Agilent Pin Scale

This results in minimal measurement overhead and higher throughput. Per-pin software licenses for speed and memory depth mean you add just the performance you need, when you need it.

With 32 pins on the Pin Scale digital card, an Agilent can be configured with up to pins, providing the pin count needed for multi-site test of even high pin count devices.

Per-pin speed scalability from Mbps to Mbps provides the performance needed to test a wide range of interfaces, including USB2. Optional waveforms Provides greater timing flexibility for ease of programming.

Add this document to collection s.

Add Upload document Create flashcards. Add to collection s Add to saved. Testing in higher x-modes means that more logical vector memory is available. As test needs change to accommodate a new class of device or next-generation performance, the Pin Scale can be instantly reconfigured through software to maximize the lifetime of your investment.

Per-pin scalability from to Mbps The test system can be configured to match device requirements, pin-by-pin, for lowest cost. Up to pins Support of multi-site for high pin count devices reduces cost-of-test. The entire amount of purchased memory is available for both test vectors and sequencer instructions, which provides more flexibility than architectures based upon two unshared memory areas.